How high can the HBM stacking level be? What are the technical challenges? 00:00 Intro 00:38 - Current status and future outlook of the HBM market 01:01 - Current status of 8-layer and 12-layer HBM development 01:24 - Need to increase the speed and capacity of HBM 02:34 - Measures to increase efficiency through microstructural adjustment 03:01 - Technology coordination process between end customers and memory companies 03:39 - Emphasizing the role and importance of standardization organizations 04:05 - Mass production readiness and features of 12-layer HBM 06:10 - Current status and future development direction of bump technology 09:22 - Emphasizing the importance of underfill materials and thermal management technology 11:09 - The role of TC bonding equipment and the advantages of the reflow process 12:00 - NCF technology and its applicability 13:59 - Diversity of bonding technologies and the role of equipment suppliers 15:02 - Standardization of packaging technology and comparison of technology strategies of Hynix and Samsung 18:30 - The impact of productivity and reliability on the selection of packaging technology Evaluation 20:00 - Outlook on technological limitations and their overcoming possibilities 21:04 - New thickness standards for HBM4 and their impact on the industry 25:03 - Thermal management issues and solution strategies for HBM technology 28:03 - Possibilities and application areas of hybrid bonding technology 32:36 - Customer test requirements and inspection issues for HBM products 33:25 - Inspection needs and technical challenges for HBM packaging #Kim Hak-seong #Hanyang University #Samsung Electronics #SK Hynix #Micron #HBM #MUF #NCF -------------------------------------------------------------------------------------------------- In the era of AI semiconductors, packaging powerhouses lead the market: Diellec 『2024 Advanced Semiconductor Package Innovation Technology Conference』 Wednesday, April 24, 2024, 10:00 ~ 17:00 COEX Conference Room 307 (513 Yeongdong-daero, Gangnam-gu, Seoul) (https://yelec.kr/product/thelecadvanc...) [Offline Event Overview] Event Name: 2024 Advanced Semiconductor Packaging Innovation Technology Conference Date: Wednesday, April 24, 2024, 10:00-17:00 Venue: COEX Conference Room 307 (513 Yeongdong-daero, Gangnam-gu, Seoul) Host/Organizer: The Yelec / Yelec Size: First-come, first-served 100 people Participation Fee: Pre-registration 440,000 won (VAT included) Registration Deadline: 18:00, Tuesday, April 23, 2024 (On-site registration not possible in case of early closing) Event Inquiries: The Yelec Director Sangsoo Kim [email protected] 010 5278 5958 [Note] ◦ Early closing may occur due to limited capacity in the seminar room. ◦ On-site attendees may enter in advance starting at 9:00. ◦ Presentation materials will be provided in file format only to speakers who have agreed to make them public. ◦ When depositing conference fees, please deposit under the company name or the registrant's name. (Woori Bank 1005-803-563727, Depositor: Theelec) * Presentation topics and speakers may change. * Tax invoices can only be issued by bank transfer. ◦ Confirmation of participation - Please apply after the conference ends. ◦ Cancellation information - Refunds can be requested up to 2 days before the event. No refunds will be made after that. - Individual parking is not supported. -------------------------------------------------------------------------------------------------- ※ Theelec Membership Membership Information ( • Theelec YouTube membership has been opened. ) Sign up for membership ( / @theelec9812 ) ※ Theelec Membership Benefits [Quickly watch Theelec videos] Theelec live videos and content are basically all 'free', but live replays are provided exclusively to membership members. Theelec, a media specializing in electronic components