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On November 30, the second autumn meeting of the FPGA-Systems community in 2024 took place in Moscow and online. The event was supported by YADRO, a leading Russian developer of equipment for data centers and telecom operators. Timings: 00:00 — Skipable 17:20 — Introduction by Mikhail Korobkov (FPGA-Systems) 20:50 — Introduction by Oleg Shchepetinshchikov (FPGA-Systems) 27:45 — Introduction to RTL digital system design using Chisel/Scala (Denis Muratov, YADRO) 1:13:05 — Generating intentional errors in UVM test (Andrey Efimov, Bureau 1440) 1:43:20 — Designing integrated circuits in Russian CAD systems (Nikita Malyshev, Eremex) 2:14:00 — Long break 3:18:15 — How we launched AMD GPU on FPGA with RISC-V Linux (Sergey Miroshnichenko, YADRO) 4:00:20 — Open Source Step-and-Compare: Making an Industrial Approach to RISC-V Verification Available to Everyone (Sergey Chusov, MIET Research Lab of ESC) 4:34:42 — Increasing Performance by Distorting Time: Extended Useful Skew (Alexey Mukhamatnabeev, YADRO) 5:14:20 — A Short Break 5:37:58 — Working with HDMI on FPGAs (Alexey Grebennikov) 6:22:15 — What's New at BMTI? (Mikhail Korobkov, FPGA-Systems) and Conference Closing You can find the slides at https://engineer.yadro.com/fpga-syste...