Automated testing with random errors: a universal approach for project verification

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Published on Dec 4, 2024
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When verifying many FPGA/ASIC-based systems, it is necessary to simulate not only normal operation, but also operation under erroneous influences. Andrey Efimov (Bureau 1440) spoke about a method that allows generating deliberate errors in the UVM test and automatically evaluating the results. Slides can be found at https://engineer.yadro.com/fpga-syste...

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